参数资料
型号: C8051F019-GQR
厂商: Silicon Laboratories Inc
文件页数: 2/154页
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 48TQFP
产品培训模块: Serial Communication Overview
标准包装: 500
系列: C8051F018
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 带卷 (TR)
C8051F018
C8051F019
1.1.
CIP-51
TM CPU
1.1.1.
Fully 8051 Compatible
The C8051F018/9 utilizes Silcon Labs’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible
with the MCS-51
TM instruction set. Standard 803x/805x assemblers and compilers can be used to develop software.
The core has all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex
UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR) address space, and four byte-
wide I/O Ports.
1.1.2.
Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz.
By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.3 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.3. Comparison of Peak MCU Execution Speeds
5
10
15
20
ADuC812
8051
(16MHz
clk)
Philips
80C51
(33MHz
clk)
Microchip
PIC17C75x
(33MHz
clk)
Silicon Labs
CIP-51
(25MHz clk)
MIPS
25
Rev. 1.2
10
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