参数资料
型号: C8051F019R
厂商: Silicon Laboratories Inc
文件页数: 94/154页
文件大小: 0K
描述: IC 8051 MCU 16K FLASH 48TQFP
标准包装: 1
系列: C8051F018
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1.25K x 8
电压 - 电源 (Vcc/Vdd): 2.8 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 剪切带 (CT)
其它名称: 336-1049-1
C8051F018
C8051F019
8.
CIP-51 CPU
The MCUs’ system CPU is the CIP-51.
The CIP-51 is fully compatible with the MCS-51
TM instruction set.
Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of
all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section
17), a full-duplex UART (see description in Section 16), 256 bytes of internal RAM, 128 byte Special Function
Register (SFR) address space (see Section 8.3), and four byte-wide I/O Ports (see description in Section 12). The
CIP-51 also includes on-chip debug hardware (see description in Section 19), and interfaces directly with the
MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram). The CIP-51 includes
the following features:
-
Fully Compatible with MCS-51 Instruction Set
-
25 MIPS Peak Throughput with 25MHz Clock
-
0 to 25MHz Clock Frequency
-
Four Byte-Wide I/O Ports
-
Extended Interrupt Handler
-
Reset Input
-
Power Management Modes
-
On-chip Debug Circuitry
-
Program and Data Memory Security
Figure 8.1. CIP-51 Block Diagram
DATA BUS
TMP1
TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA
BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
DATA
BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
B REGISTER
D8
ACCUMULATOR
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
Rev. 1.2
44
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