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参数资料
型号： C8051F300-GS
厂商： Silicon Laboratories Inc
文件页数： 173/178页
文件大小： 0K
描述： IC 8051 MCU 8K FLASH 14-SOIC
产品培训模块： Serial Communication Overview
标准包装： 56
系列： C8051F30x
核心处理器： 8051
芯体尺寸： 8-位
速度： 25MHz
连通性： SMBus（2 线/I²C），UART/USART
外围设备： POR，PWM，温度传感器，WDT
输入/输出数： 8
程序存储器容量： 8KB（8K x 8）
程序存储器类型： 闪存
RAM 容量： 256 x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
数据转换器： A/D 8x8b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 14-SOIC（0.154"，3.90mm 宽）
包装： 管件
产品目录页面： 622 (CN2011-ZH PDF)
配用： 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
其它名称： 336-1535-5
C8051F300/1/2/3/4/5
94
Rev. 2.9
10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
10.4.1. VDD Maintenance and the VDD monitor
1.
If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2.
Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an external VDD brownout circuit to the RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD
drops below 2.7 V.
3.
Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-
based systems, this will involve modifying the startup code added by the 'C' compiler. See your
compiler documentation for more details. Make certain that there are no delays in software
between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code
examples showing this can be found in “AN201: Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
4.
As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a
reset source inside the functions that write and erase Flash memory. The VDD monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5.
Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6.
Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
10.4.2. PSWE Maintenance
7.
Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou-
tine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
8.
Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
9.
Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
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C8051F300-GSR 功能描述:8位微控制器 -MCU 8KB 8ADC 2%osc MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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