参数资料
型号: C8051F302-GMR
厂商: Silicon Laboratories Inc
文件页数: 76/178页
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 11QFN
产品培训模块: Serial Communication Overview
标准包装: 1,500
系列: C8051F30x
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),UART/USART
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 8
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 10-VFDFN 裸露焊盘
包装: 带卷 (TR)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
Rev. 2.9
167
C8051F300/1/2/3/4/5
16.4. Register Descriptions for PCA
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 16.1. PCA0CN: PCA Control
Bit7:
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector
to the PCA interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.
Bit6:
CR: PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
Bits5–3: UNUSED. Read = 000b, Write = don't care.
Bit2:
CCF2: PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit1:
CCF1: PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
Bit0:
CCF0: PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine. This
bit is not automatically cleared by hardware and must be cleared by software.
R/W
Reset Value
CF
CR
CCF2
CCF1
CCF0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xD8
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