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参数资料
型号： C8051F305-GMR
厂商： Silicon Laboratories Inc
文件页数： 162/178页
文件大小： 0K
描述： IC 8051 MCU 2K FLASH 11QFN
产品培训模块： Serial Communication Overview
标准包装： 1,500
系列： C8051F30x
核心处理器： 8051
芯体尺寸： 8-位
速度： 25MHz
连通性： SMBus（2 线/I²C），UART/USART
外围设备： POR，PWM，WDT
输入/输出数： 8
程序存储器容量： 2KB（2K x 8）
程序存储器类型： 闪存
RAM 容量： 256 x 8
电压 - 电源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 10-VFDFN 裸露焊盘
包装： 带卷 (TR)
配用： 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
C8051F300/1/2/3/4/5
84
Rev. 2.9
9.1.
Power-On Reset
During powerup, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. An additional delay occurs before the device is released from reset; the delay decreases as the VDD
ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). For valid ramp
times (less than 1 ms), the power-on reset delay (TPORDelay) is typically less than 0.3 ms.
Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be
released from reset before VDD reaches the VRST level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a powerup was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is disabled following a
power-on reset.
Power-On
Reset
VDD
Monitor
Reset
/RST
t
volt
s
1.0
2.0
Logic HIGH
Logic LOW
T
PORDelay
V
D
2.70
2.55
V
RST
VDD
Figure 9.2. Power-On and VDD Monitor Reset Timing
9.2.
Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the VDD monitor is enabled and a software reset is performed, the
VDD monitor will still be enabled after the reset. The VDD monitor is enabled by writing a ‘1’ to the PORSF
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