参数资料
型号: C8051F930-TB
厂商: Silicon Laboratories Inc
文件页数: 21/25页
文件大小: 0K
描述: BOARD TARGET/PROTO W/C8051F930
产品培训模块: C8051F9xx Lower Power MCUs
视频文件: Designing for Low Power Operation
特色产品: C8051F91x/0x MCU Series Development Kit
标准包装: 1
类型: MCU
适用于相关产品: C8051F930
所含物品:
产品目录页面: 626 (CN2011-ZH PDF)
相关产品: 336-1467-ND - IC 8051 MCU 64K FLASH 32-QFN
336-1466-ND - IC 8051 MCU 64K FLASH 32-LQFP
其它名称: 336-1472
C8051F93x/92x
11. When the missing clock detector is enabled, why does the MCU reset if I switch from the default
system clock (Low Power Oscillator divided by 8) to smaRTClock divided by 1?
Background:
—The missing clock detector will trigger a reset if the system clock period exceeds 100 μs.
—Switchover between clock sources occurs in 1 clock cycle of the slowest clock.
—Changing the clock divide value requires up to 128 cycles of the undivided clock source.
Since the clock source change occurs in a single cycle and the clock divide change can take up to 128
cycles, the system clock will be set to the new clock source divided by the old divide value for a brief
period of time. In this example, the actual system clock will be 4.096 kHz for up to 128 cycles of the
undivided clock source. This causes the missing clock detector to time out and reset the MCU.
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
a. Change the clock divide value.
b. Poll for CLKRDY > 1.
c. Change the clock source .
If switching from a fast “undivided” clock to a slower “undivided” clock:
d. Change the clock source .
e. Change the clock divide value.
f. Poll for CLKRDY > 1.
12. Why is the MCU prematurely released from reset when using a wall supply with a slow rise time?
The maximum VDD Ramp Time is specified at 3 ms. If the power supply ramp takes longer than 3 ms to
reach 0.9 V, then the device may be released from reset before the supply has reached the minimum
operating voltage. The slow ramp time (>3 ms) can occur when using a bench power supply that does not
have an output enable switch.
Rev. 0.6
21
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