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参数资料
| 型号： | C9531CT |
| 英文描述： | ST7262 - LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI |
| 中文描述： | CPU系统时钟发生器| TSSOP封装| 28脚|塑料 |
| 文件页数： | 5/14页 |
| 文件大小： | 176K |
| 代理商： | C9531CT |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 5 of 14
APPROVED PRODUCT
C9531
START CONDITION
Transmit
Receive
STOP CONDITION
START CONDITION
Transmit
Receiv
STOP CONDITION
1
8
ACK
MSB
0
0
0
SDATA
0
1
LSB
COMMAND BYTE
1
SCLK
1
BYTE N
8
8
8
BYTE 0
BYTE COUNT
ACK
ACK
ACK
ACK
(Don't Care)
(Don't Care)
(Valid)
(Valid)
Fig.5a
(WRITE)
(Valid)
SDATA
1
0
(Valid)
0
1
1
8
BYTE N
(Valid)
BYTE COUNT
SCLK
LSB
ACK
8
ACK
ACK
8
0
BYTE1
1
ACK
ACK
MSB
8
1
(Valid)
BYTE 0
Fig.5b (READ)
Fig.5
Serial Control Registers
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only after true power up event occurs.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “
Command Code
“
byte, and
2) “
Byte Count
” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Byte 0: Function Select Register
Bit
@Pup
7
1
6
0
5
1
4
0
3
0
2
0
1
0
0
1
Pin#
-
15
-
7
6
-
-
-
Description
Test Mode Enable. 1=normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0=OFF, 1=ON
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table below for clarification
S1 Bank A MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
S0 Bank A LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
Not used
Not used
Hardware/SMBus frequency control. 1=Hardware (pins 6, 7, and 15), 0=SMBus Byte 0 bits 3, 4, and 6
Clarification Table for Byte0, bit5
Byte 0, bit6
Byte0, bit5
0
0
1
1
Description
Frequency generated from second PLL
Frequency generated from XIN
Spread @ -1.0%
Spread @ -0.5%
0
1
0
1
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