Low EMI Clock Generator for Pentium II CPU Systems
with Power Management
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07049 Rev. **
05/03/2001
Page 1 of 11
APPROVED PRODUCT
C9801
Product Features
Supports Intel Pentium II CPU designs.
133 and 100 Mhz CPU clock support
Designed to meet Intel chipset specification
4 CPU clocks with isolated power supply
2 CPU/2 clock with isolated power supply
8 PCI clocks with isolated power supply
3 IOAPIC clocks with isolated power supply
One 48 MHz fixed clock for USB/Super IO with
isolated power supply
4 3V66 clocks with isolated power supply
2 reference clocks with isolated power supply
<175 pS Max. skew among CPU clocks
<500 pS Max. skew among PCI clocks
Power management control of CPU and PCI clocks
56-pin SSOP package
Spread Spectrum EMI reduction mode
Block Diagram
REF
OSC
Xin
Xout
REF[0:1]
IOAPIC[0:2]
SEL[0:1]
SEL133/100#
CPU[0:3]
PCI [1:7], F
3V66 [0:3]
PLL2
48M
CS#
PS#
PD#
PLL1
VDDF
VDDA
VDDP
VDDC
VDDI
VDDF
CPU_(0:1)/2
Frequency Table
SEL133/100#
0
1
*See complete table on page 3.
CPU
100*
133*
PCI
33.3*
33.3*
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
REF1
VDD
XIN
REF0
VSS
XOUT
VSS
PCI_F
PCI1
VDDP
PCI2
PCI3
VSS
PCI4
PCI5
VDDP
PCI6
PCI7
VSS
VSS
3V66_0
3V66_1
VDDA
VSS
3V66_2
3V66_3
VDDA
SEL1
SEL0
SS#
PD#
CS#
PS#
VDD
VSS
CPU0
VSS
VDDC
CPU1
VSS
CPU3
CPU2
VDDC
CPU_1/2
VSS
CPU_0/2
VDDC
VSS
IOAPIC0
IOAPIC1
IOAPIC2
VDDI
C
VSS
28
SEL133/100#
48M
VDDF
49
50
51
52
53
54
55
56