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参数资料
| 型号： | C9805CYB |
| 英文描述： | Quad line receivers |
| 中文描述： | CPU系统时钟发生器 |
| 文件页数： | 2/10页 |
| 文件大小： | 102K |
| 代理商： | C9805CYB |
C9805
Low EMI Clock Generator for Pentium
II CPU Systems with Power Management
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
http://www.imicorp.com
Rev 1.5
9/2/1999
Page 2 of 10
Pin Description
PIN
No.
4
Pin
Name
Xin
PWR
I/O
TYPE
Description
VDD
I
OSC1
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
On-chip reference oscillator output pin. Drives an external
parallel resonant crystal when an externally generated reference
signal is used, is left unconnected
Clock outputs. CPU frequency table specified on page 1.
5
Xout
VDD
O
OSC1
36, 37,
40
43
7, 8,
10, 11,
12, 13,
15,
1618,
19
6, 14,
20, 26,
33, 35,
39, 42,
45, 48
9, 17
CPU(0:2)
VDDC
0
BUF1
CPU/2
PCI (0:9)
VDDC
VDDP
O
O
BUF4
BUF4
CPU Synchronous clock. Its frequency is half CPU clocks.
PCI bus clocks. See frequency select table on page 1.
VSS
-
P
-
Ground pins for the device.
VDDP
-
P
-
3.3 Volt power supply pins for PCI and PCI_F clock output
buffers.
3.3 Volt power supply pins for 48 MHz clock output buffers.
2.5 Volt power supply pins for IOAPIC clock buffers.
3.3 or 2.5 Volt power supply pins for CPU clock output buffers.
Power supply pins for analog circuits and core logic.
3.3 Volt power supply pins for 3V66 clock output buffers.
Fixed 66.6 Mhz Advanced Graphics Processor Clock. This clock
is rising edgy synchronous with the CPU clock.
Buffered outputs of on-chip reference oscillator.
Fixed 48 MHz frequency clock output.
CPU frequency select pin.
By design this input does not
contain any internal pullup or pulldown resistor.
Device power down signal. Removes power from all internal
logic when at a logic low level. See page 4.
3.3 Volt power supply pins for REF clock output buffers.
Function selector pins. See description on page 3.
28
47
VDD48
VDDI
VDDC
VDD
VDD66
3V66 (0:2)
-
-
-
P
P
P
-
-
-
38, 41
34
24
21, 22,
23
1, 2
27
25
-
P
O
-
VDDA
BUF
REF (0:1)
48M
SEL133/
100#
PD#
VDDR
VDDF
-
O
O
I
BUF#
BUF3
PAD
32
PU
3
VDDR
SEL (0:1)
PU
PAD
PU
PAD
PU
PAD
29, 30
-
I
31
SS#
-
I
When driven to a logic low level, this pin enables EMI reducing
Spread Spectrum mode (affects only CPU and PCI clocks).
2.5013.3 volt copy of a 16.67 Mhz clock that is synchronized with
the CPU clock. See note on page 3
46
IOAPIC
VDDI
0
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