参数资料
型号: CAT1025WI-42-GT3
厂商: ON Semiconductor
文件页数: 12/20页
文件大小: 0K
描述: IC SUPERVISR CPU 2K EEPROM 8SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 最小为 130 ms
电压 - 阀值: 4.25V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
CAT1024, CAT1025
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to V CC , the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 10. Immediate Address Read Timing
READ OPERATIONS
ˉ ˉ
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
the R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
SCL
BUS ACTIVIT Y:
MASTER
SDA LINE
8
S
T
A
R
T
S
SLAVE
ADDRESS
9
A
C
K
DATA
N
O
A
C
K
S
T
O
P
P
SDA
8TH BI T
Doc. No. MD-3008 Rev. R
DATA OUT
12
NO ACK
STOP
? 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
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