参数资料
型号: CAT1027ZI-45-GT3
厂商: ON Semiconductor
文件页数: 10/19页
文件大小: 0K
描述: IC SUPERVISOR CPU 2K EEPR 8MSOP
标准包装: 3,000
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 130 ms
电压 - 阀值: 4.5V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
CAT1026, CAT1027
ACKNOWLEDGE
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT1026 and CAT1027 respond with an
acknowledge after receiving a START condition and its
slave address. If the device has been selected along with a
When the CAT1026 and CAT1027 begin a READ mode
it transmits 8 bits of data, releases the SDA line and monitors
the line for an acknowledge. Once it receives this
acknowledge, the CAT1026 and CAT1027 will continue to
transmit data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a STOP
condition.
write operation, it responds with an acknowledge after
receiving each 8 ? bit byte.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8 ? bit address
that is to be written into the address pointers of the device.
After receiving another acknowledge from the Slave, the
SD A
SCL
START BIT
Master device transmits the data to be written into the
addressed memory location. The CAT1026 and CAT1027
acknowledge once more and the Master generates the STOP
condition. At this time, the device begins an internal
programming cycle to non ? volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
STOP BIT
Figure 6. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
STA RT
Figure 7. Acknowledge Timing
ACKNOWLEDGE
Default Configuration
1
0
1
0
0
0
0
R/W
Figure 8. Slave Address Bits
http://onsemi.com
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