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参数资料
| 型号： | CAT1027ZI-45-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 2K EEPR 8MSOP |
| 标准包装： | 3,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.5V，可调 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
CAT1026, CAT1027
S
T
S
BUS ACTIVITY:
MASTER
SDA LINE
A
R
T
S
SLAVE
ADDRESS
A
C
DATA
N
O
T
O
P
P
K
A
C
K
SCL
SDA
8
8TH BIT
9
DATA OUT
NO ACK
STOP
Figure 11. Immediate Address Read Timing
Immediate/Current Address Read
The CAT1026 and CAT1027 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid data.
After the CAT1026 and CAT1027 receive its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8 ? bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave address
S
again, this time with the R/W bit set to one. The CAT1026
and CAT1027 then respond with its acknowledge and send
the 8 ? bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
initial 8 ? bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more data.
The CAT1026 and CAT1027 will continue to output an 8 ? bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from address N
followed by data from address N + 1. The READ operation
address counter increments all of the CAT1026and
CAT1027 address bits so that the entire memory array can
be read during one operation.
S
T
T
S
BUS ACTIVITY:
MASTER
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
A
R
T
SLAVE
ADDRESS
T
O
P
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
DATA n
N
O
A
C
Figure 12. Selective Read Timing
http://onsemi.com
12
K
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