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参数资料
| 型号： | CAT1320WI-42-T3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR W/MEM 4.25V 8SOIC |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAT1320WI-42-T3DKR CAT1320WI-42-TE13DKR CAT1320WI-42-TE13DKR-ND |
CAT1320, CAT1321
Immediate/Current Address Read
The CAT1320 and CAT1321 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1320 and CAT1321 receives its
slave address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8 ? bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1320 and CAT1321 acknowledges, the Master
device sends the START condition and the slave address
again, this time with the R/W bit set to one. The CAT1320
and CAT1321 then responds with its acknowledge and sends
the 8 ? bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
initial 8 ? bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1320 and CAT1321 will continue to output an 8 ? bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1320 and
CAT1321 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1320 and
CAT1321 address bits so that the entire memory array can
be read during one operation.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
BYTE ADDRESS
A15–A8 A7–A0
S
T
A
R
T
SLAVE
ADDRESS
DATA
S
T
O
P
****
SDA LINE
* = Don’t Care Bit
S
A
C
K
S
A A
C C
K K
Figure 11. Selective Read Timing
A
C
K
N
O
A
C
K
P
S
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
T
O
P
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
Figure 12. Sequential Read Timing
http://onsemi.com
12
K
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