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参数资料
| 型号： | CAT1320YI-42-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 10/18页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR I2C 32K EEPR 8TSSO |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAT1320, CAT1321
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8 ? bit
address bytes that are to be written into the address pointers
of the device. After receiving another acknowledge from the
SD A
SCL
START BIT
Slave, the Master device transmits the data to be written into
the addressed memory location. The CAT1320/21
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non ? volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
STOP BIT
Figure 5. Start/Stop Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
STA RT
Figure 6. Acknowledge Timing
ACKNOWLEDGE
Default Configuration
1
0
1
0
A2
A1
A0
R/W
Figure 7. Slave Address Bits
Page Write
The CAT1320/21 writes up to 64 bytes of data in a single
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to
additional 63 bytes. After each byte has been transmitted, the
CAT1320/21 will respond with an acknowledge and
If the Master transmits more than 64 bytes before sending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1320/21 in a single write cycle.
internally increment the lower order address bits by one. The
high order bits remain unchanged.
http://onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1320YI-42-T3 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320YI45 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Rail/Tube |
| CAT1320YI-45-GT3 | 功能描述:监控电路 CPU SUP W/32K EEPROM RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| CAT1320YI-45-T3 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-25-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
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