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| 型号： | CAT1320YI-42-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/18页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR I2C 32K EEPR 8TSSO |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAT1320, CAT1321
DEVICE OPERATON
Reset Controller Description
The CAT1320/21 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with opendrain
RESET/RESET outputs.
During power ? up, the RESET/RESET output remains
active until V CC reaches the V TH threshold and will continue
driving the outputs for approximately 200 ms (t PURST ) after
reaching V TH . After the t PURST timeout interval, the device
will cease to drive the reset output. At this point the reset
output will be pulled up or down by their respective pull
up/down resistors.
During power ? down, the RESET/RESET outputs will be
active when V CC falls below V TH . The RESET/RESET
output will be valid so long as V CC is > 1.0 V (V RVALID ). The
device is designed to ignore the fast negative going V CC
transient pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a high to low
transition.
When RESET I/O is driven to the active state, the 200 ms
timer will begin to time the reset interval. If external reset is
shorter than 200 ms, Reset outputs will remain active at least
200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
Hardware Data Protection
The CAT1320/21 family has been designed to solve many
of the data corruption issues that have long been associated
with serial EEPROMs. Data corruption occurs when
incorrect data is stored in a memory location which is
assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output is active, in
progress communications to the EEPROM are aborted and
no new communications are allowed. In this condition an
internal write cycle to the memory can not be started, but an
in progress internal non ? volatile memory write cycle can
not be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5 ms) before VCC reaches the minimum value
of 2 V.
t GLITCH
V TH
V RVALID
V CC
t PURST
t RPD
t PURST
t R P D
RESET
RESET
Figure 1. RESET/RESET Output Timing
http://onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1320YI-42-T3 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320YI45 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Rail/Tube |
| CAT1320YI-45-GT3 | 功能描述:监控电路 CPU SUP W/32K EEPROM RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
| CAT1320YI-45-T3 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-25-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
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