- 您现在的位置：买卖IC网 > PDF目录298900 > CAT24AA01WI-T3 (ON SEMICONDUCTOR) 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 PDF资料下载
参数资料
| 型号： | CAT24AA01WI-T3 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8 |
| 文件页数： | 10/13页 |
| 文件大小： | 143K |
| 代理商： | CAT24AA01WI-T3 |
CAT24AA01, CAT24AA02
Doc. No. MD-1120 Rev. C
6
2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave
address with the R/W
bit set to ‘0’. The Master then
sends an address byte and a data byte and concludes
the session by creating a STOP condition on the bus.
The Slave responds with ACK after every byte sent by
the Master (Figure 5). The STOP starts the internal
Write cycle, and while this operation is in progress
(tWR), the SDA output is tri-stated and the Slave does
not acknowledge the Master (Figure 6).
Page Write
The Byte Write operation can be expanded to Page
Write, by sending more than one data byte to the
Slave before issuing the STOP condition (Figure 7).
Up to 16 distinct data bytes can be loaded into the
internal Page Write Buffer starting at the address
provided by the Master. The page address is latched,
and as long as the Master keeps sending data, the
internal byte address is incremented up to the end of
page, where it then wraps around (within the page).
New data can therefore replace data loaded earlier.
Following the STOP, data loaded during the Page
Write session will be written to memory in a single
internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress,
the Slave will not acknowledge the Master. This
feature enables the Master to immediately follow-up
with a new Read or Write request, rather than wait for
the maximum specied Write time (tWR) to elapse.
Upon receiving a NoACK response from the Slave,
the Master simply repeats the request until the Slave
responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is
left oating or is grounded, it has no impact on the
Write operation. The state of the WP pin is strobed on
the last falling edge of SCL immediately preceding the
1
st data byte (Figure 8). If the WP pin is HIGH during
the strobe interval, the Slave will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24AA01/02 is shipped erased, i.e., all
bytes are FFh.
相关PDF资料 |
PDF描述 |
|---|---|
| CAT24C01BGZE-1.8TE13REV-A | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| CAT24C01BJE-1.8TE13REV-A | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| CAT24C01BWE-TE13REV-A | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| CAT24C01BYI-1.8REV-A | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| CAT24C01BZA-TE13REV-A | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT24AA02 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:1-Kb and 2-Kb I2C CMOS Serial EEPROM |
| CAT24AA02TDI-10 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:1-Kb and 2-Kb I2C CMOS Serial EEPROM |
| CAT24AA02TDI-3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:1-Kb and 2-Kb I2C CMOS Serial EEPROM |
| CAT24AA02TDI-G10 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:1-Kb and 2-Kb I2C CMOS Serial EEPROM |
| CAT24AA02TDI-G3 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:1-Kb and 2-Kb I2C CMOS Serial EEPROM |
发布紧急采购，3分钟左右您将得到回复。