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参数资料
| 型号： | CAT24C043P-30 |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封装： | PLASTIC, DIP-8 |
| 文件页数： | 2/12页 |
| 文件大小： | 85K |
| 代理商： | CAT24C043P-30 |
CAT24C163/083/043/023
10
Advanced
Doc. No. 25080-00 3/98 M-1
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 10. Selective Read Timing
Figure 11. Sequential Read Timing
24C1601Fig.9
24C1601Fig.10
Immediate/Current Address Read
The CAT24CXXX’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E= 255 for
24C023, E=511 for 24C043, E=1023 for 24C083 and
E=2047 for 24C163) then the counter will ‘wrap around’
to address 0 and continue to clock out data. After the
CAT24CXXX receives its slave address information
(with the R/
W bit set to one), it issues an acknowledge,
then transmits the 8-bit byte requested. The master
device does not send an acknowledge, but will generate
a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/
W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an ac
knowledge which tells the device it requires more data.
The CAT24CXXX will continue to output an 8-bit byte for
each acknowledge sent by the Master. The operation
will terminate when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24CXXX is output-
ted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 255 for 24C023,
E=511 for 24C043, E=1023 for 24C083 and E=2047 for
24C163) bytes are read out, the counter will ‘wrap
around’ and continue to clock out data bytes.
does not send an acknowledge but will generate a STOP
condition.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT24C043P-30TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT24C043P-42TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT24C043P-45TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT24C043PA25TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT24C043PA-28TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
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