参数资料
| 型号： | CAT24C08LI-G |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT 400KHZ 8DIP |
| 标准包装： | 50 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (1K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 807 (CN2011-ZH PDF) |
| 其它名称： | 24C08LI-G |
CAT24C01, CAT24C02, CAT24C04, CAT24C08, CAT24C16
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24Cxx will interpret this as a request for data
residing at the current byte address in memory. The
CAT24Cxx will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24Cxx
returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation.
The Master device first performs a ‘dummy’ write operation
by sending the START condition, slave address and byte
address of the location it wishes to read. After the
CAT24Cxx acknowledges the byte address, the Master
device resends the START condition and the slave address,
this time with the R/W bit set to one. The CAT24Cxx then
responds with its acknowledge and sends the requested data
byte. The Master device does not acknowledge the data
(NoACK) but will generate a STOP condition (Figure 11).
Sequential Read
If during a Read session, the Master acknowledges the 1 st
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wrap ? around at end of memory (rather than end of page). In
the CAT24C01, the internal address count will not wrap
around at the end of the 128 byte memory space.
SCL
BUS ACTIVITY:
MASTER
SLAVE
8
S
T
A
R
T
S
SLAVE
ADDRESS
A
C
K
9
D ATA
BYTE
N
O
S
A T
C O
K P
P
SDA
8 th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
S
T
A
R
T
SLAVE
ADDRESS
N
O
S
A T
C O
K P
S
S
P
SLAVE
A
C
K
A
C
K
A
C
K
D ATA
BYTE
Figure 11. Selective Read Sequence
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
S
A T
C O
K P
P
SLAVE
A
C
K
D ATA
BYTE
n
D ATA
BYTE
n+1
D ATA
BYTE
n+2
D ATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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| CAT24C08WE-G | 制造商:ON Semiconductor 功能描述: |
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