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参数资料
| 型号： | CAT24C256ZD2IGT2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM I2C SRL 256KB 8TDFN |
| 产品变化通告： | 1Q2012 Discontinuation 30/Mar/2012 |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN（2x3） |
| 包装： | 带卷 (TR) |
CAT24C256
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
° C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than ? 0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than ? 1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
N END (Notes 3, 4)
T DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
3. Page Mode, V CC = 5 V, 25 ° C.
4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are re ? programmed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS ? Mature Product (Rev D)
( V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, and V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C, unless otherwise speci ? ed.)
Symbol
I CCR
I CC
Parameter
Read Current
Write Current
Test Conditions
Read, f SCL = 400 kHz
Write, f SCL = 400 kHz
Min
Max
1
3
Units
mA
mA
I SB
Standby Current
All I/O Pins at GND or V CC
T A = ? 40 ° C to +85 ° C
1
m A
T A = ? 40 ° C to +125 ° C
2
I L
I/O Pin Leakage
Pin at GND or V CC
T A = ? 40 ° C to +85 ° C
1
m A
T A = ? 40 ° C to +125 ° C
2
V IL
V IH
V OL1
V OL2
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V CC ≥ 2.5 V, I OL = 3.0 mA
V CC < 2.5 V, I OL = 1.0 mA
? 0.5
V CC x 0.7
V CC x 0.3
V CC + 0.5
0.4
0.2
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS ? Mature Product (Rev D)
(V CC = 2.5 V to 5. 5 V, T A = ? 40 ° C to +125 ° C, and V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C, unless otherwise speci ? ed.)
Symbol
C IN (Note 5)
C IN (Note 5)
I WP (Note 6)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V IN = 0 V
V IN = 0 V
V IN < V IH , V CC = 5.5 V
Max
8
6
130
Units
pF
pF
m A
V IN < V IH , V CC = 3.3 V
V IN < V IH , V CC = 1.8 V
V IN > V IH
120
80
1
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively strong;
therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source. The
variable WP input impedance is available only for Die Rev. C and higher.
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