参数资料
| 型号： | CAT24M01XI-T2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/14页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1MB I2C SER 8SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1M (128K x 8) |
| 速度： | 100kHz，400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAT24M01XI-T2OSDKR |
CAT24M01
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT24M01 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1st memory byte, etc.
When, following a START, the CAT24M01 is presented
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired two byte address. Instead of following up
with data, the Master then issues a 2nd START, followed by
the ‘Immediate Address Read’ sequence, as described
earlier.
Sequential Read
If the Master acknowledges the 1st data byte transmitted
by the CAT24M01, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap ? around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
BUS ACTIVITY: A
S
T
MASTER R
T
SDA LINE S
SLAVE
ADDRESS
S
T
O
P
P
A
C
K
DATA
N
O
A
C
K
SCL
SDA
8
8th Bit
9
DATA OUT
NO ACK
STOP
Figure 10. Immediate Address Read Timing
BUS ACTIVITY: A
S
T
MASTER R
T
SLAVE
ADDRESS
BYTE ADDRESS
a 15 ? a 8 a 7 ? a 0
S
T
A
R
T
SLAVE
ADDRESS
DATA
S
T
O
P
SDA LINE S
S
P
A
C
K
A A
C C
K K
Figure 11. Selective Read Timing
A
C
K
N
O
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
S
T
O
P
SDA LINE
P
A
C
K
A A
C C
K K
Figure 12. Sequential Read Timing
A
C
K
N
O
A
C
K
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