参数资料
| 型号： | CAT25128YI-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 128KB SPI SER 8TSSOP |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128K (16K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAT25128
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16 ? bit address (see Table 14 for the number
of significant address bits).
After receiving the last address bit, the CAT25128 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
Reading the additional 64 ? byte Identification Page (IP) is
achieved using the same Read command sequence as used
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A5:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
CS
address register defined by [A5:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 64 ? byte page
boundary.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25128 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle. While the
internal write cycle is in progress, the RDSR command will
output the full content of the status register (New product,
Rev. E) or the RDY (Ready) bit only (i.e., data out = FFh) for
previous product revisions C, D (Mature product). For easy
detection of the internal write cycle completion, both during
writing to the memory array and to the status register, we
recommend sampling the RDY bit only through the polling
routine. After detecting the RDY bit “0”, the next RDSR
instruction will always output the expected content of the
status register.
0
1
2
3
4
5
6
7
8
9
10
20 21
22 23
24
25
26 27
28 29
30
SCK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
A N
A 0
SO
HIGH IMPEDANCE
7
6
5
DATA OUT
4 3 2
1
0
CS
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 14)
Figure 9. READ Timing
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
SO
HIGH IMPEDANCE
7
6
5
4
DATA OUT
3
2
1
0
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
http://onsemi.com
11
相关PDF资料 |
PDF描述 |
|---|---|
| 346-020-522-204 | CARDEDGE 20POS DUAL .125 GREEN |
| 346-020-522-202 | CARDEDGE 20POS DUAL .125 GREEN |
| 346-020-522-201 | CARDEDGE 20POS DUAL .125 GREEN |
| 346-020-521-804 | CARDEDGE 20POS DUAL .125 GREEN |
| 346-020-521-802 | CARDEDGE 20POS DUAL .125 GREEN |
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