参数资料
型号: CAT25320YI-GT3
厂商: ON Semiconductor
文件页数: 4/19页
文件大小: 0K
描述: IC EEPROM SER 32KB 10MHZ 8TSSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 32K (4K x 8)
速度: 10MHz
接口: SPI 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 标准包装
产品目录页面: 808 (CN2011-ZH PDF)
其它名称: CAT25320YI-GT3DKR
CAT25320
Table 6. A.C. CHARACTERISTICS ? MATURE PRODUCT
(T A = ? 40 ° C to +85 ° C (Industrial) and T A = ? 40 ° C to +125 ° C (Extended).) (Notes 4, 7)
V CC = 1.8 V ? 5.5 V / ? 40 5 C to +85 5 C
V CC = 2.5 V ? 5.5 V / ? 40 5 C to +125 5 C
V CC = 2.5 V ? 5.5 V
? 40 5 C to +85 5 C
Symbol
f SCK
Parameter
Clock Frequency
Min
DC
Max
5
Min
DC
Max
10
Units
MHz
t SU
t H
t WH
t WL
t LZ
t RI (Note 5)
t FI (Note 5)
t HD
t CD
t V
t HO
t DIS
t HZ
t CS
t CSS
t CSH
t CNS
t CNH
t WPS
t WPH
t WC (Note 6)
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
40
40
75
75
0
10
0
50
20
30
50
50
10
100
50
2
2
75
50
100
5
20
20
40
40
0
10
0
20
15
20
15
15
10
60
25
2
2
40
20
25
5
ns
ns
ns
ns
ns
m s
m s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V CC to 0.7 V CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V CC
Output load: current source I OL max /I OH max ; C L = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t CSH timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the t CSH is defined relative to the negative clock edge.
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