参数资料
型号: CAT93C56VI-GT3
厂商: ON Semiconductor
文件页数: 8/17页
文件大小: 0K
描述: IC EEPROM 2KBIT 2MHZ 8SOIC
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K(256 x 8 或 128 x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: CAT93C56VI-GT3OSDKR
CAT93C56, CAT93C57
Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t CSMIN . The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C56/57
can be determined by selecting the device and polling the
DO pin. Since this device features Auto ? Clear before write,
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t CSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SaK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
it is NOT necessary to erase a memory location before it is
written into.
SK
t CSMIN
CS
STATUS
VERIFY
STANDBY
DI
1
0
1
A N
A N ? 1
A 0
D N
D 0
DO
HIGH ? Z
t SV
BUSY
READY
t HZ
HIGH ? Z
t EW
Figure 5. Write Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
A N
A N ? 1
A 0
t CS
DI
1
1
1
DO
HIGH ? Z
t SV
BUSY
READY
t HZ
HIGH ? Z
t EW
Figure 6. Erase Instruction Timing
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