参数资料
型号: CAV24C32WE-GT3
厂商: ON Semiconductor
文件页数: 7/10页
文件大小: 0K
描述: EEPROM I2C SER 32KB I2C 8SOIC
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 32K (4K x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: CAV24C32WE-GT3OSDKR
CAV24C32
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
To read data residing at a speci ? c address, the selected
address must ? rst be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
SCL
BUS ACTIVITY
MASTER
SLAVE
8
S
T
A
R
T
S
SLAVE
ADDRESS
A
C
K
9
DATA
BYTE
N
O
S
A T
C O
K P
P
SDA
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY: S
T
A
MASTER R
T
SLAVE
ADDRESS
ADDRESS
BYTE
ADDRESS
BYTE
S
T
A
R
T
SLAVE
ADDRESS
N
O
A
C
K
S
T
O
P
S
S
P
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
DATA
BYTE
Figure 11. Selective Read Sequence
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
P
SLAVE
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
Figure 12. Sequential Read Sequence
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