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| 型号： | CAV24C32YE-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM I2C SRL 32KB 8TSSOP |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 32K (4K x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAV24C32
Table 4. PIN IMPEDANCE CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unles s otherwise speci ? ed.)
Symbol
C IN (Note 4)
C IN (Note 4)
I WP (Note 5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V IN = 0 V, T A = 25 ° C, V CC = 5.0 V
V IN = 0 V, T A = 25 ° C, V CC = 5.0 V
V IN < V IH , V CC = 5.5 V
Max
8
6
130
Units
pF
pF
m A
V IN < V IH , V CC = 3.3 V
V IN < V IH , V CC = 2.5 V
V IN < V IH
120
80
2
I A (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
V IN < V IH , V CC = 5.5 V
V IN < V IH , V CC = 3.3 V
50
35
m A
V IN < V IH , V CC = 2.5 V
V IN > V IH
25
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively
strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
Table 5. A.C. C HARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C , unless otherwise specified.) (Note 6)
Standard
Fast
Symbol
Parameter
Min
Max
Min
Max
Units
F SCL
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
t F (Note 6)
t SU:STO
t BUF
t AA
t DH
T i (Note 6)
t SU:WP
t HD:WP
t WR
t PU (Notes 7, 8)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power ? up to Ready Mode
4
4.7
4
4.7
0
250
4
4.7
100
0
2.5
100
1000
300
3.5
100
5
1
0.6
1.3
0.6
0.6
0
100
0.6
1.3
100
0
2.5
400
300
300
0.9
100
5
1
kHz
m s
m s
m s
m s
m s
ns
ns
ns
m s
m s
m s
ns
ns
m s
m s
ms
ms
6.
7.
8.
Test conditions according to “AC Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t PU is the delay between the time V CC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITION S
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V CC to 0.8 x V CC
≤ 50 ns
0.3 x V CC , 0.7 x V CC
0.5 x V CC
Current Source I OL = 3 mA; C L = 100 pF
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