参数资料
型号: CC2480A1RTC
厂商: Texas Instruments
文件页数: 26/48页
文件大小: 0K
描述: IC Z-ACCEL ZIGBEE PROC 48-VQFN
产品培训模块: RFID Technology and Applications
标准包装: 260
系列: CC2480
频率: 2.4GHz
数据传输率 - 最大: 115kBaud
调制或协议: 802.15.4 Zigbee
应用: AMR,ISM,SRD
功率 - 输出: 0dBm
灵敏度: -92dBm
电源电压: 2 V ~ 3.6 V
电流 - 接收: 27mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 托盘
配用: EZ430-RFZACC06-ND - EZ430-RFZACC06
296-23357-ND - KIT DEMO FOR CC2480
其它名称: 296-23580
CC2480
In addition to the input pins A0-1, the output of
It is also possible to select a voltage
an on-chip
temperature
sensor
can be
corresponding to AVDD_SOC/3 as an ADC
selected
as
an input
to the ADC for
input. This input allows the implementation of
temperature measurements.
e.g. a battery monitor in applications where
this feature is required.
9.3.2.4
ADC Operating Modes
This section describes the operating modes
and initialization of conversions.
The ADC uses an internal voltage reference
for single-ended conversions.
The decimation rate (and thereby also the
resolution and time required to complete a
conversion and sample rate) is configurable
from 7-12 bits.
9.3.2.5
ADC Conversion Results
The digital conversion result is represented in
two's complement form. The result is always
positive. This is because the result is the
difference between ground and input signal
For differential configurations the difference
between the pins is converted and this
difference can be negatively signed. For 12-bit
resolution the digital conversion result is 2047
which
is always posivitely
signed
when the analog input, Vconv, is equal to
(Vconv=Vinp-Vinn,
where
Vinn=0V).
The
VREF, and the conversion result is -2048
maximum value is reached when the input
amplitude is equal VREF, the internal voltage
reference.
when the analog input is equal to –VREF.
9.3.2.6
ADC Reference Voltage
The positive reference voltage for analog-to-
digital conversions is an internally generated
1.25V voltage.
9.3.2.7
ADC Conversion Timing
The ADC is run on the 32MHz system clock,
which is divided by 8 to give a 4 MHz clock.
The time required to perform a conversion
depends on the selected decimation rate.
When the decimation rate is set to for instance
128, the decimation filter uses exactly 128 of
the 4 MHz clock periods to calculate the result.
When a conversion is started, the input
multiplexer is allowed 16 4 MHz clock cycles to
settle in case the channel has been changed
since the previous conversion. The 16 clock
cycles settling time applies to all decimation
rates. Thus in general, the conversion time is
given by:
Tconv = (decimation rate + 16) x 0.25 μ s.
CC2480 Data Sheet SWRS074
Page 26 of 43
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