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参数资料
| 型号： | CDB4354 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 5V DAC 2VRMS LINEDVR |
| 标准包装： | 1 |
| DAC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | I²S，串行 |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4354 |
| 产品目录页面： | 757 (CN2011-ZH PDF) |
| 其它名称： | 598-1809 CDB4354-ND |
16
DS895F2
CS4354
When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reaches
a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the
digital circuitry. Once the VA supply reaches the secondary threshold, Von2, the POR circuit releases the
internal reset.
When power is removed and the VA voltage reaches a defined threshold, Voff, the POR circuit asserts the
internal reset low, resetting all of the digital circuitry.
Note:
For correct operation of the internal POR circuit, the voltage on VL must rise before or simulta-
neously with VA.
4.8
Initialization
When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization
sequence. In this state, the AOUTx pins are weakly pulled to ground and FILT+ is connected to GND.
The device will remain in the reset state until VON2 is reached. Once VON2 is reached, the internal digital
circuitry is reset and the DAC enters a power-down state until MCLK is applied.
Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-
es the capacitors for the negative voltage supply.
Once LRCK is valid, the number of MCLK cycles is counted relative to the LRCK period to determine the
MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation filters
and delta-sigma modulators are turned on, the internal voltage reference, FILT+, powers up to normal op-
eration, the analog output pull-down resistors are removed, and power is applied to the output amplifiers.
If a valid SCLK is applied, the device will clock in data according to the applied SCLK. If no SCLK is present,
the device will clock in data using the derived internal SCLK (see Figure 3 on page 9) and will apply the de-
emphasis filter according to Section 4.4.2.1 on page 14.
After this power-up state sequence is complete, normal operation begins and analog output is generated.
If valid MCLK, LRCK, and SCLK are applied to the DAC before VON2 is reached, the total time from VON2
to the analog audio output from AOUTx is less than 50 ms.
See Figure 9 for a diagram of the device’s states and transition conditions.
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