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参数资料
| 型号： | CDB4384 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 19/52页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4384 DAC |
| 标准包装： | 1 |
| DAC 的数量： | 8 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4384 |
| 产品目录页面： | 757 (CN2011-ZH PDF) |
| 相关产品： | CS4384-CQZR-ND - IC DAC 8CH 103DB 192KHZ 48-LQFP 598-1062-ND - IC DAC 8CH 103DB 192KHZ 48LQFP |
| 其它名称： | 598-1525 |
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26
DS620F1
CS4384
4.7
ATAPI Specification
The CS4384 implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 9 on page 43 and Figure 21 for additional informa-
tion.
4.8
Direct Stream Digital (DSD) Mode
In Software Mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode. The
DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The
first method uses a decimation free DSD processing technique which allows for features such as matched
PCM level output, DSD volume control, and 50kHz on chip filter. The second method sends the DSD data
directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data
input. In this mode the DSD_PM_Mode bit selects whether a 128Fs or 64x clock is used for phase modu-
lated 64x data (see Figure 22). Use of Phase Modulation Mode may not directly effect the performance of
the CS4384, but may lower the sensitivity to board level routing of the DSD data signals.
The CS4384 can detect errors in the DSD data which does not comply with the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4384 to alter the incoming invalid DSD data.
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the
MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).
More information for any of these register bits can be found in the “Parameter Definitions” on page 49.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation
index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however,
performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital vol-
ume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There
is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output
levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
ΣΣ
A Channel
Volume
Control
Aout Ax
AoutBx
Left Channel
Audio Data
Right Channel
Audio Data
BChannel
Volume
Control
MUTE
SDINx
Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDB4385 | 功能描述:音频 IC 开发工具 Eval Bd 8-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
| CDB4390 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit, Stereo D/A Converter for Digital Audio |
| CDB4391 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit, 192 kHz Stereo DAC with Volume Control |
| CDB4391A | 功能描述:音频 IC 开发工具 Eval Bd CS4391A RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
| CDB4392 | 功能描述:音频 IC 开发工具 Eval Bd 114dB 192kHz DAC w/DSD RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
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