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参数资料
| 型号： | CDB4384 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 22/52页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4384 DAC |
| 标准包装： | 1 |
| DAC 的数量： | 8 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4384 |
| 产品目录页面： | 757 (CN2011-ZH PDF) |
| 相关产品： | CS4384-CQZR-ND - IC DAC 8CH 103DB 192KHZ 48-LQFP 598-1062-ND - IC DAC 8CH 103DB 192KHZ 48LQFP |
| 其它名称： | 598-1525 |
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DS620F1
29
CS4384
Figure 25. Recommended Mute Circuitry
4.12
Recommended Power-Up Sequence
4.12.1
Hardware Mode
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the
registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2.
Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.12.2
Software Mode
1.
Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2.
Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
3.
In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the
format and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware Mode and begin to operate with the M0-M4 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit
can not be set in time then the SDINx pins should remain static low (this way no audio data can be
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