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参数资料
| 型号： | CDB4392 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 40/40页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS4392 |
| 标准包装： | 1 |
| DAC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| DAC 型： | 电压 |
| 工作温度： | -10°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4392 |
| 相关产品： | 598-1065-5-ND - IC DAC 24BIT 192KHZ W/VC 20TSSOP |
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CS4392
DS459PP3
9
3. APPLICATIONS
3.1
Recommended Power-up Sequence for Hardware Mode
1) Hold RST low until the power supplies, master, and left/right clocks are stable.
2) Bring RST high. After 10ms the device will begin normal operation.
3.2
Recommended Power-up Sequence and Access to Control Port Mode
1) Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the control
port is reset to its default settings and FILT+ will remain low.
2) Bring RST high. The device will remain in a low power state with FILT+ low and the control port is
accessible.
3) Write 30h to register 05h within 10 ms cycles following the release of RST. If after 10ms the control
port has not been initiated with this command, the device will enter stand-alone mode. The CPEN bit,
however, may be written at any time after 10ms. It is recommended to write CPEN before 10ms in or-
der to reduce the possibility of any extraneous click or pop noise from occurring.
4) The desired register settings can be loaded while keeping the PDN bit set to 1.
5) Set the PDN bit to 0. This will initiate the power-up sequence which requires approximately 10 S.
3.3
Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter as seen in Figure 3. An alternate configuration
can be seen on the CDB4392. This alternate filter configuration accounts for the differing AC loads on the
+ and - differential output pins which are normally present in a circuit like Figure 3. It also shows an AC
coupling configuration which reduces the number of required AC coupling capacitors to 2 caps per chan-
nel. The circuit in figure 3 may also be DC coupled, however the filter on the CDB4392 must be
AC coupled. The CS4392 is a linear phase design and does not include phase or amplitude compensation
for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the
external analog circuitry.
3.01k
1.58k
3.01k
10 uF
560
1.58k
10 uF
3.32k
+
-
3
2
1
R17
3.32k
10 uF
680 pF
C10
680 pF
2700 pF
47k
Aout -
Aout +
Analog_Out
Figure 3. CS4392 Output Filter
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