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参数资料
| 型号： | CDB5368 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 7/19页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5368 192KHZ ADC |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| 输入范围： | ±0.3 V |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | CS5368 |
| 已供物品： | 板，线缆 |
| 产品目录页面： | 756 (CN2011-ZH PDF) |
| 相关产品： | CS5368-DQZ-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP CS5368-CQZR-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP 598-1090-ND - IC ADC 8CH 114DB 216KHZ 48-LQFP |
| 其它名称： | 598-1157 |
DS624F4
15
CS5368
SERIAL AUDIO INTERFACE - IS/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; CL = 20 pF, timing threshold is 50% of VLS.
Notes:
1.
Duty cycle of generated SCLK depends on duty cycle of received MCLK as specified under “System
2.
CLKMODE functionality described in Section 4.6.3
3.
In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, chip performance
is guaranteed only when using the ratios in Section 4.7 Master and Slave Clock Frequencies on page
Figure 3. IS/LJ Timing
Parameter
Symbol
Min
Typ
Max
Unit
Sample Rates
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
-
2
54
108
-
54
108
216
kHz
Master Mode
SCLK Frequency
SCLK Period
1/(64*216 kHz)
SCLK Duty Cycle (Note 1)
(CLKMODE = 0)(Note 2)
(CLKMODE = 1)(Note 2)
-
tPERIOD
tHIGH
64*Fs
72.3
40
28
-
50
33
64*Fs
-
60
38
Hz
ns
%
LRCK setup
before SCLK rising
LRCK hold
after SCLK rising
tSETUP1
tHOLD1
20
--
ns
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tHOLD2
10
20
10
5
--
ns
Slave Mode
SCLK Frequency (Note 3)
SCLK Period
1/(64*216 kHz)
SCLK Duty Cycle
-
tPERIOD
tHIGH
-
72.3
28
64*Fs
-
65
Hz
ns
%
LRCK setup
before SCLK rising
LRCK hold
after SCLK rising
tSETUP1
tHOLD1
20
--
ns
SDOUT setup
before SCLK rising (VLS = 1.8 V)
before SCLK rising (VLS = 3.3 V)
before SCLK rising (VLS = 5 V)
SDOUT hold
after SCLK rising (VLS = 1.8 V)
after SCLK rising (VLS = 3.3 V)
after SCLK rising (VLS = 5 V)
tSETUP2
tHOLD2
4
10
20
10
5
--
ns
LRCK
SDOUT
SCLK
data
channel
data
t
HOLD2
t
SET UP2
t
HOLD1
t
SET UP1
t
PERIOD
t
HIGH
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相关代理商/技术参数 |
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| CDB5374 | 功能描述:音频 IC 开发工具 2-Ch DS Modulator & Hydrophone Demo Brd RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
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| CDB5376Z | 制造商:Cirrus Logic 功能描述:PB-FREE EVAL BD LOW-POWER, MULTICH DECIMATION FILTER - Bulk |
| CDB5378 | 功能描述:音频 IC 开发工具 Eval Bd LP Mult-Ch Decimation Filter RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
| CDB5378Z | 制造商:Cirrus Logic 功能描述:PB-FREE EVAL BD LOW-POWER, MULTICH DECIMATION FILTER - Bulk |
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