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参数资料
| 型号： | CH5001A-L |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS COLOR DIGITAL VIDEO CAMERA |
| 中文描述： | CMOS彩色数码摄像机 |
| 文件页数： | 4/34页 |
| 文件大小： | 136K |
| 代理商： | CH5001A-L |
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4
201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
CH5001A
Table 1. Pin Descriptions
Pin
Type
Out
Symbol
Description
21-14
Y[7:0]
Video Output
Provides the luminance data of the digital video output.
7, 11, 22, 34
Power
DVDD
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH5001.
4, 8, 24, 36
Power
DGND
Digital Ground
Provides the ground reference for the digital section of CH5001. These
pins MUST be connected to the system ground.
32-25
Out
C[7:0]
Video Output
Chrominance data of the digital video output are provided by these
pins.
33
Out
CRS
Cr Select
CRS specifies the CrCb data sequence. CRS is an alternating signal.
CRS=1 indicates that C[7:0] carry the Cr data. CRS=0 indicates C[7:0]
carry the Cb data.
23
Out
CLKOUT
Video Pixel Clock Output
This pin outputs a buffered clock signal which can be used to latch data
output by pins Y[7:0] and C[7:0].
9
Out
VS*
Vertical Sync Output (active low)
Outputs a vertical sync pulse.
10
Out
HS*
Horizontal Sync Output (active low)
Outputs a horizontal sync pulse.
12
Out
OVR
Over Range
This pin is high when the A/D converter input is beyond the full scale
range of the A/D.
13
Out
HREF
Horizontal Reference
Active video timing signal. This output is high when active data is being
output from the device, and low otherwise.
6
In
SC
Serial Clock
IIC clock input pin.
5
In/Out
SD
Serial Data
IIC data input/output pin.
2
In
AS
Chip Address Select (internal pullup)
This pin selects the IIC address for the device.
AS = 1 Address = 100 0101
AS = 0 Address = 100 0110
3
In
RESET*
Chip Reset (active low, internal pullup)
Puts all registers into power-on default states. The state at pin SD must
be HIGH during reset for proper initialization.
38
In/Out
XO
Crystal Output
A 27 MHz (± 50 ppm, parallel resonance) crystal may be attached
between XO and XI/FIN.
39
In
XI/FIN
Crystal Input or External input
A 27 MHz (± 50 ppm, parallel resonance) crystal should be attached
between XO and XI/FIN. An external CMOS compatible clock can be
connected to XI/FIN as an alternative.
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