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| 型号： | CMOD232+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | EVAL SYSTEM FOR MAX9850 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
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MAX9850
Status Registers (0x0, 0x1)
Alert Flag (ALERT)
1 = An interrupt event has occurred.
0 = No interrupt event has occurred.
ALERT is an alert flag that sets when an interrupt event
has occurred. The events that can be programmed to
set ALERT are as follows:
A change in state on SGPIO indicating a change in
levels at GPIO when GPIO is configured as an input.
Configure GPIO as an input and set ISGPIO = 1 in
the interrupt enable register (register 0x4, bit B6).
The internal PLL locks or unlocks with LRCLK. Set
ILCK = 1 in the interrupt enable register (register
0x4, bit B5).
A change in state on SHPS indicating headphones
have been connected or disconnected. Set ISHPS =
1 in the interrupt enable register (register 0x4, bit B4).
The headphone amplifier reaches its minimum vol-
ume. Set IVMN = 1 in the interrupt enable register
(register 0x4, bit B3).
An overload on either right or left headphone out-
puts (HPR, HPL). Set IIOH = 1 in the interrupt
enable register (register 0x4, bit B0).
ALERT sets to 1 after an event occurs and remains set
until the status A register is read. GPIO configured as an
output can interrupt a C on an ALERT event. GM(1:0) in
the GPIO register (register 0x3, bits B7 and B6) control
the output mode of GPIO. See the GPIO section for more
information on programming GPIO as an output.
GPIO Status (SGPIO)
1 = GPIO is high.
0 = GPIO is low.
SGPIO reports the status of GPIO at the time that status
A is read, regardless of whether GPIO is programmed
as an input or output. A change in state on SGPIO
causes ALERT to set to 1 when GPIO is configured as
an input and ISGPIO = 1 in the interrupt enable register
(register 0x4, bit B6).
PLL Lock Status (LCK)
1 = The internal PLL is locked with LRCLK.
0 = The internal PLL is not locked with LRCLK.
LCK reports the lock status of the internal PLL at the
time that STATUS A is read. The DAC is disabled when
the PLL is not locked. When the PLL is locked with
LRCLK, the DAC will become operational if DACEN is
equal to 1 (register 0x5, bit B0). ALERT sets to 1 when
LCK changes state if ILCK = 1 in the interrupt enable
register (register 0x4, bit B5).
HPS Status (SHPS)
1 = HPS is high, indicating that headphones are con-
nected.
0 = HPS is low, indicating no headphone is connected.
SHPS reports the debounced status of HPS at the time
STATUS A is read. SHPS = 0 indicates that no head-
phone is connected and HPS is low. SHPS sets to 1 when
HPS is high, indicating headphones are connected.
ALERT sets to 1 when SHPS changes state, if ISHPS = 1
in the interrupt enable register (register 0x4, bit B4).
Volume at Minimum (VMN)
1 = Headphone volume has reached its minimum volume.
0 = Headphone volume is not at its minimum.
VMN sets to 1 when the minimum headphone amplifier
volume has been reached. ALERT sets to 1 when IVMN
= 1 in the interrupt enable register (register 0x4, bit B3).
Headphone Overcurrent Left (IOHL)
1 = The left headphone output (HPL) has experienced
an overcurrent condition.
0 = The left headphone output (HPL) is operating normally.
IOHL sets to 1, when an overcurrent occurs on the left
headphone output HPL and remains set until status A is
read. ALERT sets to 1 when an overcurrent on the right
or left headphone output occurs if IIOH = 1 in the inter-
rupt enable register (register 0x4, bit B0).
Headphone Overcurrent Right (IOHR)
1 = The right headphone output (HPR) has experi-
enced an overcurrent condition.
0 = The right headphone output (HPR) is operating normally.
IOHR sets to 1 and remains set until STATUS A is read.
ALERT sets to 1 when an overcurrent on the right or left
headphone output occurs if IIOH = 1 in the interrupt
enable register (register 0x4, bit B0).
Stereo Audio DAC with DirectDrive
Headphone Amplifier
22
______________________________________________________________________________________
Table 10. Status A (0x0) Read-Only, Bit
Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
ALERT SGPIO
LCK
SHPS
VMN
1
IOHL
IOHR
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