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| 型号： | COP8CBR9KMT8 |
| 厂商： | National Semiconductor |
| 文件页数： | 48/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 标准包装： | 34 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 49 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 包装： | 管件 |
| 其它名称： | *COP8CBR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-11. Register and Bit Name Definitions
Register
RAM
Purpose
Name
Location
ISPADHI
High byte of Flash Memory Address
0xA9
ISPADLO
Low byte of Flash Memory Address
0xA8
ISPWR
The user must store the byte to be written into this register before jumping into the write byte
0xAB
routine.
ISPRD
Data will be returned to this register after the read byte routine execution.
0xAA
ISPKEY
The ISPKEY Register is required to validate the JSRB instruction and must be loaded within 6
0xE2
instruction cycles before the JSRB.
BYTECOUNTLO
Holds the count of the number of bytes to be read or written in block operations.
0xF1
PGMTIM
Write Timing Register. This register must be loaded, by the user, with the proper value before
0xE1
execution of any USER ISP Write or Erase operation. Refer to Table 5-7 for the correct value.
Confirmation Code
The user must place this code in the accumulator before execution of a Flash Memory Mass Erase
A
command.
KEY
Must be transferred to the ISPKEY register before execution of a JSRB instruction.
0x98
5.10.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM
1. The hardware will disable interrupts from occurring. The hardware will leave the GIE bit in its current
state, and if set, the hardware interrupts will occur when execution is returned to Flash Memory.
Subsequent interrupts, during ISP operation, from the same interrupt source will be lost. Interrupts
may occur between setting the KEY and executing the JSRB instruction. In this case, the KEY
will expire before the JSRB is executed. It is, therefore, recommended that the software globally
disable interrupts before setting the Key.
2. The security feature in the MICROWIRE/PLUS ISP is ensured by software and not hardware. When
executing the MICROWIRE/PLUS ISP routine, the security bit is checked prior to performing all
instructions. Only the mass erase command, write PGMTIM register, and reading the Option register is
permitted within the MICROWIRE/PLUS ISP routine. When the user is performing his own ISP, all
commands are permitted. The entry points from the user's ISP code do not check for security. It is the
burden of the user to ensure his own security. See the Security bit description in Option Register for
more details on security.
3. When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG
within the selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the
lower window is enabled, and the user can service the WATCHDOG anytime following exit from Boot
ROM, but must service it within the selected upper window to avoid a WATCHDOG error.
4. Block Writes can start anywhere in the page of Flash memory, but cannot cross half page or full page
boundaries.
5. The user must ensure that a page erase or a mass erase is executed between two consecutive
writes to the same location in Flash memory. Two writes to the same location without an
intervening erase will produce unpredicatable results including possible disturbance of
unassociated locations.
5.10.10 FLASH MEMORY DURABILITY CONSIDERATIONS
The endurance of the Flash Memory (number of possible Erase/Write cycles) is a function of the erase
time and the lowest temperature at which the erasure occurs. If the device is to be used at low
temperature, additional erase operations can be used to extend the erase time. The user can determine
how many times to erase a page based on what endurance is desired for the application (e.g. four page
erase cycles, each time a page erase is done, may be required to achieve the typical 100k Erase/Write
cycles in an application which may be operating down to 0°C). Also, the customer can verify that the entire
page is erased, with software, and request additional erase operations if desired.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
41
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