参数资料
型号: COP8CBR9LVA8
厂商: National Semiconductor
文件页数: 84/111页
文件大小: 0K
描述: IC MCU EEPROM 8BIT 32K 68PLCC
标准包装: 18
系列: COP8™ 8C
核心处理器: COP8
芯体尺寸: 8-位
速度: 20MHz
连通性: Microwire/Plus(SPI),UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 59
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 68-LCC(J 形引线)
包装: 管件
其它名称: *COP8CBR9LVA8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-23 shows the Interrupt block diagram.
Figure 5-23. Interrupt Block Diagram
5.15.2 MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated
enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The state
of the interrupt enable bit, combined with the GIE bit determines whether an active pending flag actually
triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped
control registers, and thus can be controlled by the software.
A maskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced,
a maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of these conditions are met at the beginning of an instruction. If
different maskable interrupts meet these conditions simultaneously, the highest-priority interrupt will be
serviced first, and the other pending interrupts must wait.
74
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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