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参数资料
| 型号： | COP8SGR928V9 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的内存，2个比较器和USART |
| 文件页数： | 62/62页 |
| 文件大小： | 913K |
| 代理商： | COP8SGR928V9 |
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AC Electrical Characteristics (Continued)
Note 4: Maximum rate of voltage change must be < 0.5 V/ms.
Note 5: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, External Oscillator, inputs connected to VCC and outputs driven low
but not connected to a load.
Note 6: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced high internally. In the crystal
or external configuration, CKI is TRI-STATE. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with L. F, C, G0, and G2–G5
programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to VCC; clock monitor disabled. Parameter refers
to HALT mode entered via setting bit 7 of the G Port data register.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when
biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750 (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes
ESD transients.
Note 8: National Semiconductor uses the High Temperature Storage Life (HTSL) test to evaluate the data retention capabilities of the EPROM memory cells used
in our OTP microcontrollers. Qualification devices have been stressed at 150C for 1000 hours. Under these conditions, our EPROM cells exhibit data retention
capabilities in excess of 29 years. This is based on an activation energy of 0.7eV derated to 55C.
Note 9: Parameter characterized but not tested.
Note 10: Rise times faster than the minimum specification may trigger an internal power-on-reset.
Note 11: MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock. See and the MICROWIRE
operation description.
Comparators AC and DC Characteristics
V
CC = 5V, 40C ≤ TA ≤ +85C.
Parameter
Conditions
Min
Typ
Max
Units
Input Offset Voltage (Note 12)
0.4V
≤ V
IN ≤ VCC 1.5V
±5
±15
mV
Input Common Mode Voltage Range
0.4
V
CC 1.5
V
Voltage Gain
100
dB
Low Level Output Current
V
OL = 0.4V
1.6
mA
High Level Output Current
V
OH =VCC 0.4V
1.6
mA
DC Supply Current per Comparator
(When Enabled)
150
A
Response Time (Note 13)
200 mV step input
100 mV Overdrive,
100 pF Load
600
ns
Comparator Enable Time(Note 14)
600
ns
Note 12: The comparator inputs are high impedance port inputs and, as such, input current is limited to port input leakage current.
Note 13: Response time is measured from a step input to a valid logic level at the comparator output. software response time is dependent of instruction execution.
Note 14: Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the output of the
comparator, either by hardware or by software.
10131709
FIGURE 3. MICROWIRE/PLUS Timing
COP8SG
Family
www.national.com
9
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