参数资料
| 型号： | COREFFT-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 1/15页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFFT |
| 标准包装： | 1 |
| 系列： | * |
CoreFFT Fast Fourier Transform
Product Summary
Synthesis and Simulation Support
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Actel Libero IDE
Intended Use
? Fast Fourier Transform (FFT) Function for Actel
FPGAs
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Synthesis: Synplicity, ? Synopsys ? (Design Compiler /
FPGA Compiler), Exemplar?
Simulation: OVI-Compliant Verilog Simulators and
Vital-Compliant VHDL Simulators
Key Features
Contents
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Forward and Inverse 32-, 64-, 128-, 256-, 512-,
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?
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?
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1,024-, and 2,048-Point Complex FFT
Decimation–In-Time (DIT) Radix-2 Implementation
Optimized for Actel FPGAs
Selection of Unconditional or Conditional Block
Floating-Point Scaling
Embedded RAM-Block-Based Twiddle Factor
Generator
8- to 16-Bit Configurable Input/Output Data and
Twiddle Coefficients Precision
Naturally Ordered Input and Output Data
Two’s-Complement Fixed-Point Arithmetic
Built-In Memory Buffers
CoreFFT Provides Register Transfer Level (RTL)
Code and a Behavioral Testbench
References ................................................................ 11
Targeted Devices
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ProASIC ? 3/E
ProASIC PLUS?
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Axcelerator ?
RTAX-S
General Description
CoreFFT is an RTL generator that produces an Actel
FPGA–optimized FFT engine. The resulting module
Core Deliverables
? Full Version
computes 32-, 64-, 128-, 256-, 512-, 1,024-, or 2,048-point
complex forward or inverse decimation-in-time (DIT)
FFTs. The input and output data is represented as bb -bit
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CoreFFT RTL Generator; Generates User-
Defined FFT Model and Test Harness; Fully
Supported in Actel Libero ? Integrated Design
Environment (IDE)
words comprising b -bit real and imaginary parts
( bb = b + b ; b = 8 to 16 bits). Both the real and imaginary
parts of the input and output data are two’s-
complement numbers. The FFT module contains all the
?
Evaluation Version
necessary memory buffers and butterfly and control
–
May 2007
Supports FFT Engine and Test Harness
Generation with Limited Parameters; Fully
Supported in Actel Libero IDE
v 4 .0
logic, as well as a twiddle factor generator. A dual input
buffer and a single output buffer support simultaneous
input of the new data samples with FFT computation and
result output. The module processes frames (bursts) of
data with a frame size equal to the transform size of N
words. The FFT computational process occurs in a
1
? 2007 Actel Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFFT-RMFL | 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1 |
| COREFFT-UR | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| COREFIR-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-RM | 功能描述:IP MODULE COREFIR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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