参数资料
| 型号： | COREFFT-RM |
| 厂商： | Microsemi SoC |
| 文件页数： | 6/15页 |
| 文件大小： | 0K |
| 描述： | IP MODULE COREFFT |
| 标准包装： | 1 |
| 系列： | * |
CoreFFT Fast Fourier Transform
The radix-2 butterfly processes the data according to the DIT algorithm, [1] one pair of samples per clock. The Write
Switch works similarly to the Read Switch, rearranging the butterfly results prior to being written back to the in-place
memory bank.
On the last stage of every FFT computational cycle, the results are written into the output memory buffer rather than
back to the in-place memory bank. Figure 3 shows the FFT computational sequence.
FFT Cycle i
FFT Stages
FFT Cycle i + 1
FFT Stages
1
2
3
...
log 2 N
1
2
3
...
log 2 N
Ping-Pong Input Buffer
Ping bank is busy.
Pong bank is available for loading input data.
Output Buffer
Ping-Pong Input Buffer
Ping bank is available for loading input data.
Pong bank is busy.
Output Buffer
Available for reading results of cycle (i – 1)
Accepts
FFT result
Available for reading results of cycle i
Accepts
FFT result
Figure 3 ? FFT Computational Sequence
Every FFT stage takes
the minimal read sample rate to avoid FFT engine idle
(N / 2 + L) clock cycles
to complete, where
EQ 1
time is
(N / 2 + L) (log 2 N – 1) / N ≈ (log 2 N – 1) / 2 clock cycles
EQ 4
N/2
= the number of butterflies
performed within a stage
to
be
As a result, the minimal input and output sample rates
required to avoid FFT engine idle time depend on the
transform size N ( Table 4 ).
L
= an implementation-specific parameter
representing the aggregate latency of the
Table 4 ? Minimal Input and Output Sample Rates
memory bank, switches, and butterfly. L is
Transform Size
Input Sample
Output Sample
much less than the number of butterflies
N, Points
Rate, Clock Cycles Rate, Clock Cycles
required (N / 2) and does not depend on
transform size N.
The full FFT cycle takes
(N / 2 + L) log 2 N clock cycles.
256
512
1,024
4
4
5
3
4
4
EQ 2
This time is available for the new frame of N data
samples to be loaded into the memory bank not involved
in the current FFT computation. To provide maximum FFT
engine utilization (no idle time, FFT engine full loading),
the minimal input sample rate that the host should
provide is
Finite Word Length
Considerations
The butterfly calculation involves complex multiplication,
addition, and subtraction. These operations can
potentially cause the butterfly data width to grow by
((N / 2 + L) log 2 N) / N ≈ (log 2 N) / 2 clock cycles
EQ 3
two bits from input to output. [1], [2] At every stage of the
in-place FFT algorithm, the butterfly takes two samples
out of the input buffer and returns two processed
The host can read the output buffer during the first
log 2 N – 1 stages of the next FFT computational cycle (the
last stage is used to write fresh FFT results). Therefore,
samples to the same buffer location. Potentially,
returning samples may have a larger data width than the
6
v4.0
相关PDF资料 |
PDF描述 |
|---|---|
| COREFIR-RM | IP MODULE COREFIR |
| COREPCIF-RM | IP MODULE COREPCIF |
| COREU1LL-AR | IP MODULE COREU1LL |
| COREU1PHY-AR | IP MODULE COREU1PHY |
| CORR-8BIT-XM-UT2 | SITE LICENSE IP CORRELATOR XP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COREFFT-RMFL | 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1 |
| COREFFT-UR | 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1 |
| COREFIR-AR | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-EV | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreFIR Finite Impulse Response (FIR) Filter Generator |
| COREFIR-RM | 功能描述:IP MODULE COREFIR RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
发布紧急采购，3分钟左右您将得到回复。