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参数资料
| 型号： | CORR-8BIT-P2-U2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 6/10页 |
| 文件大小： | 0K |
| 描述： | DEV IP CORE CORRELATOR ECP2 CONF |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | CORR8BITP2U2 |
Lattice Semiconductor
Correlator IP Core
block can be a maximum of 36 bits wide, therefore if the number of correlator cells (MWIDTH) is not greater than
36, only one column of EBR memories is required for the Coef?cient Memories. If MWIDTH > 36, then multiple col-
umns will be con?gured. As in the case of the Tap Memories, if the total number of coef?cients which needs to be
stored exceeds one row of EBR memories, then multiple rows will be con?gured in a stacked arrangement as
shown in Figure 4. For MWIDTH ≤ 36, the number of coef?cients required is [NUM_TAP * NUM_COEF_SEQ]. If
this number is less than 8192 then only one EBR is needed for the Coef?cient Memory.
Unlike the Tap Memories which are written with new user data under the control of the state machine, the Coef?-
cient Memories must be written with the coef?cient sequences before any correlation operations can be done. This
is done via the Coef?cient Memory Con?guration interface shown in Figure 5. This interface consists of the input
signals: coeffaddr , coeffwdat , coeffwdat_im , and coeffwr . Figure 6 shows the timing for this interface for
a two-channel design with MWIDTH=4, NUM_TAP=16 and NUM_COEF_SEQ=2.
Figure 5. Coef?cient Memory Con?guration Interface Timing
In this case, the Coef?cient Memory is implemented in one EBR block. Each row of Coef?cient Memory is required
to store MWIDTH=4 coef?cients, so each write to the memory writes four bits. Each coef?cient sequence is
NUM_TAP=16 bits long, and it will occupy (NUM_TAP / MWIDTH)= 4 rows in the Coef?cient Memory. In addition, in
this example there are two separate coef?cient sequences, so the coef?cients will occupy a total of eight rows in
the Coef?cient Memory.
Writes to the Coef?cient Memory are enabled by asserting the coeffwr input. The coeffaddr input selects the
row of memory to be written, and coeffwdat (and coeffwdat_im for complex correlations) is set to the desired
value. This is a very simple interface, however it is essential to make sure that the coef?cient sequence is written in
the correct order. In the example above, the ?rst four values written are for coef?cient sequence 0. The values writ-
ten are 0xa6fc (or in binary: 1010 0110 1111 1100) with the LSB being the ?rst bit in the correlation sequence. This
bit will be multiplied against the newest data value received by the Correlator. The MSB in this string will be multi-
plied against the oldest data read from Tap Memory. This is explained further in the Correlator Evaluation Package
section of this document.
The second coef?cient sequence written into the Coef?cient Memory is 0x0180, and is written into rows 7, 6, 5 and
4. This will be selected as coef?cient sequence 1 by setting the code_sel_in to 1 when a data value is input to
the Correlator. Figure 6 shows how the coef?cient values from this example would appear in the Coef?cient Mem-
ory:
6
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| CORR-8BIT-P2-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-PM-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-PM-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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