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参数资料
| 型号： | CORR-8BIT-PM-U2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/10页 |
| 文件大小： | 0K |
| 描述： | DEV IP CORE CORRELATOR ECP2M |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | CORR8BITPMU2 |
Lattice Semiconductor
Figure 4. Tap and Coef?cient Memories
Tap Memory
Nu m b er of Data W ords (Taps)
per Ro w of Memory = M W IDTH
Correlator IP Core
Coefficient Memory
EBR Block
EBR Block
Nu m b er of Coefficients
per Ro w of Memory = M W IDTH
Ali g ner
Correlator
Corr
Cell
Corr
Cell
Corr
Cell
Corr
Cell
Nu m b er of Correlator
Cells = M W IDTH
Tap and Coef?cient Memories
While the Tap and Coef?cient Memories are being read, the values read are passed to the Aligner. Under the con-
trol of the state machine the Aligner shifts the tap data and coef?cients to be passed to the Correlator block. The
state machine also generates strobe signals to the Aligner which indicate, in any given clock cycle, which tap and
coef?cient values are valid for the correlator block to work on.
The Tap and Coef?cient Memories are implemented with EBR blocks as shown in Figure 4. The Correlator IP core
will automatically con?gure and instantiate the proper number of EBR blocks in the design based on the parame-
ters selected by the user. In the case of the Tap Memory, the number of correlator cells, number of taps, number of
channels, and the oversampling rate all determine how many EBR memories are needed. The number of correlator
cells (parameter MWIDTH) determines how many words of data can be operated on during a single clock cycle.
The more correlator cells which are con?gured, the more multiplication operations can occur in a clock cycle and
the overall data throughput goes up. At least one EBR memory is required to feed each correlator cell. All Tap
Memory EBR blocks in the design will be con?gured to be at least the word width of the input data (DWIDTH) wide.
The EBR blocks can be sized 1, 2, 4, or 9 bits wide, and must be equal to or greater than DWIDTH. Since each
EBR block can store 8192 bits, if the value of [TAP_EBR_WIDTH * (NUM_TAP / MWIDTH) * NUM_CHAN *
OS_FACTOR] exceeds 8192 bits, then multiple EBR blocks will be stacked in columns to feed the correlator cells,
as shown in Figure 4. TAP_EBR_WIDTH is the minimum allowed EBR width which is at least DWIDTH wide. The
Tap Memory EBRs will be con?gured automatically for the user; however, the user is responsible for determining
the total number of EBR blocks needed for the design and insure that the target LatticeEC? device contains
enough memories.
The Coef?cient Memories are also implemented in EBR blocks. Since each coef?cient is constrained to be 1 bit,
the total amount of memory required for coef?cients is generally less than that required for tap data. Each EBR
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORR-8BIT-PM-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-SC-UT2 | 功能描述:开发软件 8 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-X2-U2 | 功能描述:开发软件 Correlator IP Core User Config RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CORR-8BIT-X2-UT2 | 功能描述:开发软件 BIT CORRELATOR IP RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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