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参数资料
| 型号： | CP82C52Z |
| 厂商： | Intersil |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC UART/BRG 5V 16MHZ 28-PDIP |
| 标准包装： | 143 |
| 特点： | 单芯片 UART/BRG |
| 通道数： | 1，UART |
| 规程： | RS232C |
| 电源电压： | 4.5 V ~ 5.5 V |
| 带并行端口： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 28-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 28-PDIP |
| 包装： | 管件 |
14
FN2950.3
April 26, 2006
UART Timing Characterization
All parameters listed in this table were laboratory bench characterized at room temperature on a small sample of parts. No guarantee is implied. The main intent here is
to clarify functional operation of the 82C52.
82C52 UART Timing Characterized with IX = External Clock
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(15)
TS1
CO(IX) Delay from IX
-
30
ns
BRSR Bit D7 = 0
(IX Output)
(16)
TS2
CO (BRG) Delay from IX
-
80
ns
BRSR Bit D7 = 1
(BRG Output)
(17)
TCY
CO (BRG) Clock Cycle Time
62.5
-
ns
BRSR Bit D7 = 1
(BRG Output), Note 1
(18)
TDTX
SDO Delay from CO(BRG) Low
-
30
ns
Note 2
(19)
TWLTL
WR Low to TBRE Low
-
50
ns
Note 3
(20)
TCLTH
CO (BRG) Low to TBRE HIgh
-
50
ns
Notes 3, 4
(21)
TIHF
INTR High on Flag
-
50
ns
Note 5A, 5B
(22)
TIHM
INTR High on MS
-
50
ns
Note 5
(23)
TRLIL
RD Low to INTR Low
-
60
ns
(24)
TCTHX
CTS High to Disable Transmit
4TCY + 10
-
ns
TBR Full, Note 6
(25)
TDRH
CO (BRG) Low to DR High
-
40
ns
Note 7
(26)
TRLDL
RD Low to DR Low
-
50
ns
Note 7
(27)
TWHO
WR High to RTS/DTR Active
-
50
ns
NOTES:
1. Prescaler rate of divide by 1, Divisor Select rate of “external” (divide by 1). The Baud Rate Clock (CO-BRG) operates at 16 times the user
programmed bit rate. For example, at 1200 baud: TCY = 1/(16 x 1200) = 52.1
s.
2. A. With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge
of the 12th CO(BRG) in the last Stop bit.
C. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
3. TBRE bit D6 in USR is updated each time TBRE changes state.
4. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the
trailing edge of the 12th CO(BRG) in the last Stop bit.
C. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
5. A. INT on TC: INTEN enabled; USR bit D5(TC) is updated at this time regardless of interrupt configuration.
- INT on TC occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit if TBR empty at that time.
B. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt configura-
tion.
- INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low by
the trailing edge of the 8th CO(BRG) in the last Stop bit.
C. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.
- INTR on MS occurs whenever CTS or DSR input changes state.
6. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
7. DR bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit.
82C52
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