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参数资料
| 型号： | CP82C88Z |
| 厂商： | Intersil |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | IC CMOS BUS CONTROLLER 20DIP |
| 标准包装： | 360 |
| 应用： | CMOS 总线控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 1mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 20-PDIP |
| 包装： | 管件 |
82C88
Pin Description
PIN
(Continued)
SYMBOL
AMWC
NUMBER
8
TYPE
O
DESCRIPTION
ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the machine
cycle to give memory devices an early indication of a write instruction. Its timing is the same as a read command
signal. AMWC is active LOW.
MWTC
9
O
MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on the data
bus. This signal is active LOW.
MRDC
7
O
MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data bus. MRDC
is active LOW.
INTA
14
O
INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been
acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.
MCE/PDEN
17
O
This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt sequence
and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto the data bus. The
MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables the data bus transceiver
for the I/O bus that DEN performs for the system bus. PDEN is active LOW.
Functional Description
The command logic decodes the three 80C86, 8086, 80C88,
8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to
determine what command is to be issued (see Table 1).
TABLE 1. COMMAND DECODE DEFINITION
IOB mode if I/O or peripherals dedicated to one processor
exist in a multi-processor system.
System Bus Mode
The 82C88 is in the System Bus mode if the IOB pin is
S2
0
0
0
0
S1
0
0
1
1
S0
0
1
0
1
PROCESSOR STATE
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
82C88
COMMAND
INTA
IORC
IOWC, AIOWC
None
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both I/O
and memory are shared by more than one processor.
Command Outputs
1
1
1
1
0
0
1
1
0
1
0
1
Code Access
Read Memory
Write Memory
Passive
MRDC
MRDC
MWTC, AMWC
None
The advanced write commands are made available to initiate
write procedures early in the machine cycle. This signal can
be used to prevent the processor from entering an
unnecessary wait state.
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
I/O Bus Mode
The 82C88 is in the I/O Bus mode if the IOB pin is strapped
HIGH. In the I/O Bus mode, all I/O command lines IORC,
IOWC, AIOWC, INTA) are always enabled (i.e., not
dependent on AEN). When an I/O command is initiated by
the processor, the 82C88 immediately activates the
command lines using PDEN and DT/R to control the I/O bus
transceiver. The I/O command lines should not be used to
control the system bus in this configuration because no
arbitration is present. This mode allows one 82C88 Bus
Controller to handle two external busses. No waiting is
involved when the CPU wants to gain access to the I/O bus.
Normal memory access requires a “Bus Ready” signal (AEN
LOW) before it will proceed. It is advantageous to use the
3
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
FN2979.2
August 25, 2005
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