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参数资料
| 型号： | CPC1466DTR |
| 厂商： | CLARE INC |
| 元件分类： | 通信及网络 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封装： | ROHS COMPLIANT, SOIC-16 |
| 文件页数： | 3/15页 |
| 文件大小： | 309K |
| 代理商： | CPC1466DTR |
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www.clare.com
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excellent means of indicating loop availability for
designs with a full time sealing current requirement. In
addition, for pulsed sealing current loops, the status
from this detector when used in conjuntion with the
timing of modem retraining events can be used as an
indicator to determine if the sealing current event is
clearing line impairments.
2.6 On-State Behavior
2.6.1 Typical Conditions
On-state sealing current levels are determined by the
network’s power feed circuit and the loop’s dc
impedance. To compensate for low loop resistance or
very high loop voltage, the CPC1466 limits the
maximum sealing current to 70 mA.
The CPC1466 manages package power dissipation
by shunting excess sealing current through the 2.2 k
4W power resistor located between the PR+ and PR-
pins.
2.6.2 Over-Voltage Conditions
Potentials in excess of 100 V applied to the tip and
ring interface will cause the CPC1466 to disable the
sealing current hold circuit and enter a standby state
with very little current draw. Once the over-voltage
condition is removed, the CPC1466 automatically
resumes normal operation.
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