参数资料
型号: CPC75282KATR
厂商: CLARE INC
元件分类: 通信及网络
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP44
封装: ROHS COMPLIANT, TQFP-44
文件页数: 5/19页
文件大小: 667K
代理商: CPC75282KATR
CPC75282
R00D
www.clare.com
13
2.3 Switch Logic
2.3.1 Start-up
The CPC75282 uses smart logic to monitor the VDD
supply. Any time the VDD is below an internally set
threshold, the smart logic places the control logic to
the all-off state until the LATCHx input is pulled low.
Prior to the assertion of a logic low at the LATCHx pin,
the switch control inputs must be properly conditioned.
2.3.2 Switch Timing
When switching from the ringing state to the idle/talk
state, the CPC75282 provides the ability to control the
release timing of the ringing switches, SW3 and SW4,
relative to the state of the switches, SW1 and SW2,
using simple logic inputs. The two available
techniques are referred to as make-before-break and
break-before-make operation. When the break switch
contacts of SW1 and SW2 are closed (made) before
the ringing switch contacts of SW3 and SW4 are
opened (broken), this is referred to as
make-before-break operation. Break-before-make
operation occurs when the ringing contacts of SW3
and SW4 are opened (broken) before the switch
contacts of SW1 and SW2 are closed (made).
With the CPC75282, make-before-break and
break-before-make operations can easily be
accomplished by applying the proper sequence of
logic-level inputs to the device.
The logic sequences for either mode of operation are
states and explanations are shown in “Truth Tables”
2.3.3 Make-Before-Break Operation
To use make-before-break operation, change the logic
inputs from the ringing state directly to the idle/talk
state. Application of the idle/talk state opens the
ringing return switch, SW3, as the break switches,
SW1 and SW2, close. The ringing switch, SW4,
remains closed until the next zero-crossing of the
ringing current. While in the make-before-break state,
ringing potentials in excess of the CPC75282
protection circuitry thresholds will be diverted away
from the SLIC.
2.3.4: Make-Before-Break Operation Logic Table (Ringing to Talk Transition)
State
(CFG=0, P3=0)
P2
P1
LATCHx OFFx
Timing
Break
Switches
1x & 2x
Ringing
Return
Switch
3x
Ringing
Switch
4x
Test
Switches
5x & 6x
Ringing
1
0
01
-Off
On
Off
Make-
before-
break
00
SW4 waiting for next zero-current
crossing to turn off. Maximum time is
one-half of the ringing cycle. In this
transition state current limited by the DC
break switch current limit value will be
sourced from the ring node of the SLIC.
On
Off
On
Off
Idle/Talk
0
Zero-cross current has occurred
On
Off
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