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参数资料
| 型号： | CPC7595ZCTR |
| 厂商： | CLARE INC |
| 元件分类： | 通信及网络 |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | ROHS COMPLIANT, SOIC-20 |
| 文件页数： | 10/24页 |
| 文件大小： | 658K |
| 代理商： | CPC7595ZCTR |
CPC7595
18
www.clare.com
R02
switches when pulled to a logic low. Although logically
disabled, an active (closed) ringing switch (SW4) will
remain closed until the next current zero crossing
event.
As shown in the table “Break-Before-Make Operation
operation is similar to the one shown in “Alternate
Transition)” on page 18, except in the method used to
select the all-off state and when the INRINGING,
INTESTin and INTESTout inputs are reconfigured for the
talk state.
1.
Pull TSD to a logic low to end the ringing state.
This opens the ringing return switch (SW3) and
prevents any other switches from closing.
2.
Keep TSD low for at least one-half the duration of
the ringing cycle period to allow sufficient time for
a zero crossing current event to occur and for the
circuit to enter the break before make state.
3.
During the TSD low period, set the INRINGING,
INTESTin and INTESTout inputs to the talk state
(0,0,0).
4.
Release TSD allowing the internal pull-up to
activate the break switches.
When using TSD as an input, the two recommended
states are “0” which over rides logic input pins and
forces an all-off state and “Z” which allows switch
control via the logic input pins. This requires the use of
an open-collector or open-drain type buffer.
Alternate Break-Before-Make Operation Logic Table (Ringing to Talk Transition)
2.4 Data Latch
The CPC7595 has an integrated transparent data
latch. The latch enable operation is controlled by TTL
logic input levels at the LATCH pin. Data input to the
latch are via the input pins, while the output of the data
latch are internal nodes used for state control. When
the LATCH enable control pin is at logic 0 the data
latch is transparent and the input data control signals
flow directly through the latch to the state control
circuitry. A change in input will be reflected by a
change in switch state. Whenever the LATCH enable
control pin is at logic 1, the latch is active and data is
locked. Subsequent input changes will not result in a
change to the control logic or affect the existing switch
state.
Switches will remain in the state they were in when the
LATCH pin changes from logic 0 to logic 1 and will not
respond to changes in input as long as the latch is at
logic 1. However, neither the TSD input nor the TSD
output control functions are affected by the latch
function. Internal thermal shutdown control and
external “All-off” control via TSD is not affected by the
state of the LATCH enable input.
2.5 TSD Pin Description
The TSD pin is a bi-directional I/O structure with an
internal pull up sourced from VDD. As an output, this
pin indicates the status of the thermal shutdown
circuitry. Typically, during normal operation, this pin will
be pulled up to VDD but under fault conditions that
create excess thermal loading the CPC7595 will enter
thermal shutdown and a logic low will be output.
State
INRINGING INTESTin INTESTout
Latch
TSD
Timing
Break
Switches
Ringing
Return
Switch
(SW3)
Ringing
Switch
(SW4)
Test
Switches
Ringing
1
0
Z
-
Off
On
Off
All-off
1
0
1
X0
Hold this state for at least
one-half of ringing cycle.
SW4 waiting for zero current
to turn off.
Off
On
Off
Break-
Before-
Make
00
0
Zero current has occurred.
SW4 has opened
Off
Talk
0
Z
Break switches close.
On
Off
相关PDF资料 |
PDF描述 |
|---|---|
| CPC7595BC | |
| CPC7595ZATR | |
| CPC7595MC | |
| CPC7595BCTR | |
| CPC7595ZB | |
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| CPC7691BA | 功能描述:固态继电器-PCB安装 LCAS4 w Protection SCR, TTL Inputs, High SW4 DV/DT RoHS:否 制造商:Omron Electronics 控制电压范围: 负载电压额定值:40 V 负载电流额定值:120 mA 触点形式:1 Form A (SPST-NO) 输出设备:MOSFET 封装 / 箱体:USOP-4 安装风格:SMD/SMT |
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