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| 型号： | CS1500-FSZ |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | 稳压器 |
| 中文描述： | 0.5 A POWER FACTOR CONTROLLER, 70 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封装： | 0.150 INCH, LEAD FREE, MS-012, SOIC-8 |
| 文件页数： | 13/14页 |
| 文件大小： | 201K |
| 代理商： | CS1500-FSZ |
CS1500
8
DS849F1
Nov ?$shortyear>
CONFIDENTIAL
5. GENERAL DESCRIPTION
The
CS1500
offers
numerous
features,
options,
and
functional capabilities to the designer of switching power
converters. This digital PFC control IC is designed to replace
legacy analog PFC controllers with minimal design effort.
5.1 PFC Operation
One key feature of the CS1500 is its operating frequency
profile. Figure 11 illustrates how the frequency varies over half
cycle of the line voltage in steady-state operation. When
power is first applied to the CS1500, it examines the line
voltage and adapts its operating frequency to the line voltage
as shown in Figure 11. The operating frequency is varied from
the peak to the trough of the AC input. During start-up the
control algorithm’s goal is to generate maximum power while
maintaining DCM operation, providing an approximate
square-wave envelop current within every half line cycle by
adjusting the operating frequency for fast startup behavior.
Figure 11. Switching Frequency vs. Phase Angle
Figure 12 illustrates how the operating frequency (as a
percentage of maximum frequency) changes with output
power and the peak of the line voltage.
Figure 12. Max Switching Frequency vs. Output Power
When Po falls below 5% the CS1500 changes to Burst Mode
5.2 Start-up vs. Normal Operation Mode
CS1500 has two discrete operation modes: Start-up and
Normal. Start-up mode will be activated when Vlink is less than
90% of nominal value and remains active until Vlink reaches
100% of nominal value, as shown in Figure 13. Startup mode
is activated during initial system power-up. Any Vlink drop to
less than 90% of nominal value, such as load change, can
cause the system to enter Start-up mode until Vlink is brought
back into regulation.
Figure 13. Start-up and Normal Modes
Startup mode is defined as a surge of current delivering
maximum power to the output regardless of the load. During
every active switch cycle, the 'ON' time is calculated to drive a
constant peak current over the entire line cycle. However, the
'OFF' time is calculated based on the DCM/CCM boundary
equation.
5.3 Burst Mode
Burst mode is utilized to improve system efficiency when the
system output power (Po) is < 5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period cycle under light load conditions, as shown in
Figure 14. Burst Modes
0
20
40
60
80
100
120
045
90
135
180
Rectified Line Voltage Phase (Deg.)
%
of
Max
Switching Freq. (% of Max.)
Line Voltage (% of Max.)
% PO max
F
SW
m
a
x
(k
H
z
)
Vin < 181 VAC
20
70
50
60
40
5
Bur
s
tM
o
d
e
20
0
60
80
100
Vin > 147 VAC
46
56
t [ms]
Vlink
[V]
100%
90%
S
tar
tu
p
M
od
e
Normal
Mode
S
tar
tu
p
M
od
e
Normal
Mode
Vin
[V]
t [ms]
FET
Vgs
Burst Mode
Active
Vin
Po
[W]
t [ms]
PFC
Disable
Burst Threshold
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