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CS1500
DS849F1
9
Nov ?$shortyear>
CONFIDENTIAL
5.4 Output Power and PFC Boost Inductor
In normal operating mode, the nominal output power is
estimated by the following equation.
where:
Po
rated output power of the system
η
efficiency of the boost converter (estimated as 100%
by the PFC algorithm)
Vin(min) minimum RMS line voltage is 90V, measured after
the rectifier and EMI filter
Vlink
nominal PFC output voltage must be 400 V
fmax
maximum switching frequency is 70 kHz
LB
boost inductor specified by rated power requirement
α
margin factor to guarantee rated output power (Po)
against boost inductor tolerances.
Equation 1 is provided for explanation purposes only. Using
substituted required design values for Vlink and fmax gives the
following equation.
Changing values for application-specific devices such as the
boost inductor or Vlink voltage is not recommended and
requires changing internal register values.
Solving Equation 2 for the PFC boost inductor LB gives the
following equation.:
If a value of the boost inductor other than that obtained from
Equation 3 above is used, the total output power capability as
well as the minimum input voltage threshold will differ
according to Equation 2.
Figure 15. Relative Effects of Varying Boost Inductance
5.5 PFC Output Capacitor
The value of the PFC output capacitor should be chosen
based upon voltage ripple and hold-up requirements. To
ensure system stability with the digital controller, the
recommended value of the capacitor is within the range of
0.5
μF / watt to 2.0 μF/watt.
5.6 Output IFB Sense & Input IAC Sense
A current proportional to the PFC output voltage, Vlink, is
supplied to the IC on pin IFB and is used as a feedback control
signal. This current is compared against an internal fixed-
value current.
The ADC is used to measure the magnitude of the IFB current
through resistor RIFB. The magnitude of the IFB current is then
compared to an internal fixed-value current.
Figure 16. Feedback Input Pin Model
Resistor RIFB sets the feedback current and is calculated as
follows:
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
Figure 17. IAC Input Pin Model
Resistor RIAC sets the IAC current and is derived as follows:
For optimal performance, resistors RIAC & RIFB should use 1%
tolerance or better resistors.
Po
αη
V
in min
()
×
2
×
V
link
V
in min
()
2
×
()
–
2f
max
L
B
V
link
×
---------------------------------------------------------
×
=
[Eq.1]
Po
αη
90V
()
×
2
×
400V
90V
2
×
()
–
270kHz
L
B
400V
×
-------------------------------------------------------------
×
=
[Eq.2]
L
B
αη
90V
()
×
2
×
400V
90V
2
×
()
–
270kHz
Po
400V
×
-------------------------------------------------------------
×
=
[Eq.3]
VAC(rms)
90
265
P
o(
m
a
x
)
L > LB
/α
L = LB
L < LB
/α
IFB
VDD
15k
7
Vlink
CS1500
24k
ADC
R3
RIFB
IFB
R4
4
R
IFB
V
link
V
dd
–
I
fixed
----------------------------
400V
V
dd
–
129
μA
------------------------------
==
[Eq.4]
R1
RIAC
IAC
IA C
VDD
15k
7
Vrect
CS1500
24k
ADC
R2
3
R
IAC
R
IFB
=
[Eq.5]