- 您现在的位置：买卖IC网 > PDF目录295335 > CS2200-CP-CZZR (CIRRUS LOGIC INC) PHASE LOCKED LOOP, 75 MHz, PDSO10 PDF资料下载
参数资料
| 型号： | CS2200-CP-CZZR |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, 75 MHz, PDSO10 |
| 封装： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件页数： | 5/26页 |
| 文件大小： | 307K |
| 代理商： | CS2200-CP-CZZR |
CS2200-CP
DS759PP1
13
5.2.3
Effective Ratio (REFF)
The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as
previously described. REFF is calculated as follows:
REFF = RUD
R
MOD
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example
if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the
12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the fre-
quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
5.2.4
Ratio Configuration Summary
The RUD is the user defined ratio stored in the register space. R-Mod is applied if selected. The user de-
fined ratio and ratio modifier make up the effective ratio REFF, the final calculation used to determine the
output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual
diagram in Figure 7 summarizes the features involved in the calculation of the ratio values used to gen-
erate the fractional-N value which controls the Frequency Synthesizer.
Figure 7. Ratio Feature Summary
Referenced Control
Register Location
Ratio...................................... “Ratio (Address 06h - 09h)” on page 21
RModSel[2:0] ........................ “R-Mod Selection (RModSel[2:0])” section on page 20
RefClkDiv[1:0] ....................... “Reference Clock Input Divider (RefClkDiv[1:0])” on page 22
Effective Ratio REFF
Ratio Format
SysClk
PLL Outpu
Frequency
Synthesizer
R Correction
N
Ratio
12.20
Ratio
Modifier
RModSel[2:0]
RefClkDiv[1:0]
Timing Reference Clock
(XTI/REF_CLK)
Divide
RefClkDiv[1:0]
User Defined Ratio RUD
相关PDF资料 |
PDF描述 |
|---|---|
| CS235GDWR18 | SPECIALTY ANALOG CIRCUIT, PDSO18 |
| CS3717AGNF16 | STEPPER MOTOR CONTROLLER, 1 A, PDIP16 |
| CS3972YDW16 | 3 A SWITCHING CONTROLLER, 47 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5157GD16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5165GDWR16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS2200CP-CZZR | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200CP-DZZ | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200CP-DZZR | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
发布紧急采购，3分钟左右您将得到回复。