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参数资料
| 型号： | CS2200-CP-CZZR |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, 75 MHz, PDSO10 |
| 封装： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件页数： | 6/26页 |
| 文件大小： | 307K |
| 代理商： | CS2200-CP-CZZR |
CS2200-CP
14
DS759PP1
5.3
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
Figure 8. PLL Clock Output Options
5.4
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 9, to one of three signals: refer-
ence clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
Figure 9. Auxiliary Output Selection
Referenced Control
Register Location
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis .............................. “PLL Clock Output Disable (ClkOutDis)” on page 20
Referenced Control
Register Location
AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 20
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 19
AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 22
PLL Locked/Unlocked
PLL Output
2:1 Mux
ClkOutDis
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutDis
AuxOutSrc[1:0]
AuxLockCfg
Timing Reference Clock
(RefClk)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS2200CP-CZZR | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200CP-DZZ | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200CP-DZZR | 功能描述:时钟合成器/抖动清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
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