参数资料
型号: CS4362-KQZ
厂商: Cirrus Logic Inc
文件页数: 11/42页
文件大小: 0K
描述: IC DAC 6CH 114DB 192KHZ 48LQFP
标准包装: 250
位数: 24
数据接口: 串行
转换器数目: 6
电压电源: 模拟和数字
功率耗散(最大): 390mW
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
输出数目和类型: 6 电压,单极
采样率(每秒): 200k
产品目录页面: 757 (CN2011-ZH PDF)
其它名称: 598-1644
DS257F2
19
CS4362
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change
will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently
monitored and implemented for each channel.
4.3.2
Single Volume Control (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume
Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
4.3.3
Soft Volume Ramp-Up After Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change or
error, and after changing the Functional Mode. When this feature is enabled, this un-mute is effected, sim-
ilar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register. When disabled,
an immediate un-mute is performed in these instances.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
4.3.4
MUTEC Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Note: When the on board mute circuitry is designed for active low, the MUTEC outputs will be high (un-
muted) for the period of time during reset and before this bit is enabled to 1.
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